1. Technical Field
The invention relates generally to the field of dynamic random access memory (DRAM) design, and more particularly to a DRAM architecture that provides a redundant bit decoder for particular use in block write operations. The decoder achieves efficient use of fabrication area.
2. Background Art
From the very early stages of DRAM development in the 1970's , designers have recognized the need for integral error recovery circuitry. That is, given the large number of processing steps needed to make a memory chip, and given the large number of discrete transistor-capacitor memory cells to be fabricated, from a practical standpoint it is inevitable that at least some memory cells will not function properly.
Semiconductor memories generally take the form of a memory array of elements which are accessed or selected by row and column decoders in order to address a particular memory element. A sense amplifier formed on the semiconductor chip is used to sense the memory state of the selected memory element when addressed. Typically, each memory element is connected to a bit-line. Each bit-line can be selectively coupled to a data-line, which in turn can be connected to the sense amplifier.
As the density of the memory array on a semiconductor chip increases, it becomes increasingly difficult to maintain high production yields and memory chip reliability. A prior art solution has been to provide redundant memory elements or bits in the form of additional rows or columns on the semiconductor chip which are to be substituted for defective elements in a faulty area of the memory array. U.S. Pat. No. 4,601,031 to Walker et al., U.S. Pat. No. 4,689,494 to Chen et al., U.S. Pat. No. 4,691,301 to Anderson, U.S. Pat. No. 4,791,615 to Pelley, III, et al., U.S. Pat. No. 4,827,452 to Toyama et al., U.S. Pat. No. 4,829,480 to Seo, U.S. Pat. No. 4,837,747 to Dosaka et al., U.S. Pat. No. 4,849,938 to Furutani et al., U.S. Pat. No. 4,858,192 to Tatsumi et al., and Japanese Pat. Publication No. 63-79300 are representative of such prior art.
Semiconductor memories are frequently characterized as being divided into sub-arrays or blocks of memory cells. Such block architecture is often chosen to reduce power consumption. Prior art systems, such as the U.S. Pat. No. 4,601,019 to Shah, et al., include a block architecture employing separate redundant blocks of memory elements for each sub-array. A problem with such architecture is that the redundancy is not efficiently implemented in the design, because the redundant rows and used can replace defective rows and columns in only the same sub-array as that of the redundant rows and columns. As a result, the total number of redundant elements required to provide memory reliability is greatly multiplied.
U.S. Pat. No. 4,807,191 to Flannagan proposes a solution to this problem by providing a block of redundant columns for each stack of sub-arrays in the memory module. Each block of redundant columns includes groups of four contiguous columns. Any one of these groups of four contiguous columns replaces a group of four contiguous columns containing at least one defective column found in any of the sub-arrays in the stack. When a defective column is identified, the defective column is replaced, along with the three other columns in the group, whether or not they are defective. As a result, four contiguous columns in one of the sub-arrays is replaced by four contiguous columns in the redundant sub-array. Flannagan states that the memory architecture could be modified to have only a single defective column replaced by a single redundant column, instead of always replacing four contiguous columns any time column redundancy is implemented.
Although the prior art methods described above are effective for use in normal DRAM read/write operations, the methods are inefficient for implementing redundancy in a DRAM during a block write operation. The block write operation is common to dual port RAMs, sometimes referred to as video RAMs (VRAMS). During a block write operation, data in an on-chip color register is to be written to a plurality of adjacent bit lines defined by a column address. For example, in a one megabit (1 Mb) memory module (256 Kb.times.4 VRAM), the address of four adjacent bit lines can be defined by column address bits A2-A8. The two least significant address bits A0-A1 are used only during the normal read/write operation of the memory module to select a single bit line. These address bits are replaced by four input data bits DQ0-DQ3 during the block write operation.
Normally these input data bits are used by a microprocessor coupled to the memory module to provide input data that is to be written into memory. However, during block write operation, the data bits DQ0-DQ3 are used as an address mask. More specifically, the data input bits determine which of the four column address locations decoded by address bits A2-A8 are intended to be loaded with video data during the block write cycle. The input data on DQ0 controls the write operation to the bit line normally accessed when A0 is in a low state (A0=0) and A1 is in a low state (A1=0); DQ1 controls the write operation to the bit line normally accessed when A0=1 and A1=0; DQ2 controls the write operation to the bit line normally accessed when A0=0 and A1=1; and, likewise, DQ3 controls the write operation to the bit line normally accessed when A0=1 and A1=1.
Accordingly, a need exists in the art for a memory module architecture that incorporates redundancy with a block write access capability. Moreover, there is a need in the art for a redundancy system that improves upon the production yields, memory reliability, and the area required for implementation in such a memory module.